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Differential Amplifier with Current Mirror Load

Circuit Description

Differential amplifier with current mirror load.

When we discussed a differential amplifier with active collector loads, we noted that such a circuit could not be balanced accurately, and that the circuit would have to be self-balancing to operate effectively. A practical self-balancing circuit is shown to the right.

In this circuit, Q1 and Q2 still have transistors as active collector loads, but this time Q5 and Q6 form a current mirror of their own. As a result, the reference current for Q5 is exactly the collector current of Q1, whatever that current might be. This current is mirrored by Q6, and has no other connection. Note that this does mean we can't get an output from Q1's collector, so we will have a single-ended output even though we have a differential input.

Now, let's see just how this works, assuming ideal matching and no significant base current (very high value of β). When IN1 = IN2 there is no differential input. This means that IC1 = IC2. Q5 uses IC1 as its reference current, and this current is mirrored by Q6. Therefore IC6 = IC2 and there is no current flowing into or out of OUT.

Now, let's increase IN1 enough to increase IC1 by 0.1 mA. This increases IC5 by 0.1 mA, which in turn increases IC6 by 0.1 mA. At the same time, increasing IC1 by 0.1 mA also means decreasing IC2 by 0.1 mA. As a result, there is now a difference of 0.2 mA between IC2 and IC6. This becomes the output current at OUT.

If we apply a differential input sufficient to increase IC2 by 0.1 mA, the same thing happens in reverse. IC1 decreases by 0.1 mA, thus decreasing IC5 and IC6 by 0.1 mA. This creates a 0.2 mA difference in the other direction between IC2 and IC6. Again, that difference becomes the output current.



Errors and Common Mode Gain

Of course, no circuit is perfectly ideal. Base currents and the output resistance of Q4 will have their usual effects. Also, the collector voltage of Q5 is fixed, while VCE6 can vary according to whatever load is connected at OUT. This in itself creates a mismatch between Q5 and Q6. Nevertheless, this circuit works well enough that it or a minor variation appears in many commercially-built integrated circuits (ICs). In cases where base current might be a problem, the buffered current mirror can be used in place of the basic mirror circuit.

The actual common mode gain of this circuit depends on transistor parameters, the degree of mismatch, and other factors that cause each instance of this circuit to be different from all other instances. However, the current mirror load does help to limit the effect of Q4's output resistance. As a result, common mode gain is fairly close to unity. The differential gain is much higher, so this circuit offers a very reasonable common mode rejection ratio (CMRR) for most practical applications.

In cases where the differential gain of an amplifier stage like this one is insufficient for some reason, or if a differential output is necessary, or if common mode gain must be reduced to an absolute minimum, there is one further adjustment we can make to this circuit. We'll examine it on the next page.


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