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| D Flip-Flop Using NOR Latches | D Flip-Flop Using NAND Latches | CMOS Flip-Flop Construction |

D Flip-Flop Using NAND Latches

This circuit utilizes three interconnected RS NAND latch circuits, as shown. It is identical in structure to the NOR version of the circuit, and with one exception behaves in the same way. That exception is that the output can only change state on the rising edge of the CLK signal (0 to 1 transition), where the NOR version changes state on the falling edge (1 to 0 transition).

The two input latch circuits store the D and D' signals separately, and apply those stored signals to the output latch. While the CLK input is a logic 1, changes to the D input cannot affect the states of the input latches, and is isolated from the output latch.

When CLK goes to logic 0, it inherently forces the outputs of the two middle input gates to logic 1. This effectively isolates the output latch from any input changes. Note that at this time, one or the other of the two input latches will be in an illegal state, depending on the state of the D input. This illegal state overrides the latching action of that input circuit.

Now, when CLK rises to logic 1, whichever input latch was in an illegal state will abruptly resume its latching action, and will at once control the state of the output latch. In this manner, the circuit is still an edge-triggered flip-flop that will take on the state of the D input at the moment of the rising clock edge.

Edge-triggered D NAND flip-flop

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